Boundary scan is a solution for interconnect testing between chips on printed circuit boards (PCBs).

First, traditional testing is facing the following problems: tiny components such as SMTs and BGAs lack physical access, making it difficult to probe pins on the board; SOC chip-level designs require testing of the master chip; due to the increasing complexity of ICs, ICTs are becoming longer and more expensive to develop, and designers are forced to propose a large number of test points, which is in direct conflict with miniaturization design goals. Using ICT to do in-circuit programming, slow, inefficient, high cost; Nowadays, electronic components are getting smaller and smaller, the pins are getting denser and denser, and there are more BGA/FQP/LPQ packages without exposed pins, so how do we judge the quality of the chip soldering and the circuit board SMT? Motherboards are becoming denser and more complex designs with more high-speed signals. Due to physical space constraints and loss of physical access to fine-pitch components and BGA devices, fixture costs have increased significantly while fixture reliability has decreased.

Boundary-scan testing is an ingenious approach to structural testing that overcomes the limitations of traditional testing and has been recognized as a necessary part of testing and a future trend.

Boundary scan test has two major advantages: one is to facilitate the fault location of the chip, quickly and accurately test the connection of the two chip pins is reliable, to improve the efficiency of the test inspection; the other is that, with the JTAG interface chip, built-in a number of pre-defined functional modes, through the boundary-scan channel to make the chip is in a particular functional mode to improve the flexibility of the system control and to facilitate the design of the system. Now, all complex IC chips almost all have JTAG control interface, JTAG control logic is simple and convenient, easy to realize.

Second, the principle of boundary-scan: it is in the core logic circuit input and output ports are increased by a register, by connecting these registers on the I/O, the data can be serially input into the unit under test, and read out serially from the corresponding port. In this process, it can realize 3 aspects of testing.

The first is chip-level testing, which means that the chip itself can be tested and debugged so that the chip operates in normal functional mode, and debugging can be performed by inputting test vectors through the inputs and by observing the output response of the serial shift.

Next is board-level testing, which detects the interconnections between integrated circuits and PCBs. The realization principle is to connect the scan registers in all ICs with boundary scan on a PCB together, and through certain test vectors, it can find out whether the components are missing or incorrectly placed, and at the same time, it can detect open-circuit and short-circuit faults of the pins.

Finally, the system level test can be realized by in-line programming of the on-board CPLD or Flash after board level integration.

The boundary-scan test architecture provides the ability to efficiently test components with very dense leads on the PCB. Without the use of physical test probes, the architecture can test pin connections and collect functional data under normal device operation. The boundary-scan unit in the device can force signals into pins or capture data from pins or core logic signals. Forced test data is moved serially into the boundary-scan unit. Captured data will be serially moved out and externally compared with the expected results.

Third, boundary-scan in the application of board-level test 

Boundary scan test technology is not only applied to individual chip testing, but also in the field of board testing is also widely used. As shown in the figure below, multiple ICs with compatible scanning functions can be serially interconnected on the PCB to form one or more boundary-scan chains, each with its own TAP. Each scan chain provides electrical access to the serial TAP interface to each lead on each IC as part of the chain. During normal operation, the IC performs its intended function as if the boundary-scan circuitry were not present. However, when the scan logic of the device is activated for the purpose of performing tests or programming in the system, data is transferred to the ICs through the interconnecting Test Access Ports TAP) and read from the ICs using the serial interface. Such data can be used to activate the device core, send signals from the leads TDI to the PCB, read out the input leads of the PCB and read out the TDO outputs.   Boundary scan is used in board level testing to detect and isolate faults in interconnecting wires and pins between devices on the PCB and to program in-system programmable devices.

The generalized test strategy for testing boundary-scan boards is:

1) Perform board-level boundary-scan basic structural integrity tests.

 2) Use the Extest command to apply excitation and detect responses to perform tests of the interconnections between boundary-scan devices, and set the non-boundary-scan devices to the desired state during testing.

(3) Perform tests on non-boundary-scan devices, such as cluster tests, RAM tests, etc.  In the normal operation mode, ICs with boundary-scan function do not seem to realize their specific functions. However, when it is time to test or program the system, the device's scanning logic is activated, daisy-chaining multiple devices with JTAG interfaces together to form a scan chain that achieves complete testing of the entire board using a single set of test vectors.   Boundary-scan testing is also a good choice for functional testing of circuit boards with complex surface-mount technology, as it can quickly eliminate manufacturing faults in the product and allow functional testing to truly find functional faults. Current mainstream in-circuit and flying probe test equipment also has boundary-scan test capabilities.  While many devices in use can utilize BST techniques, there are still some circuits that do not have boundary-scan capabilities. Some test equipment vendors can utilize specific software to achieve this with their in-circuit test ATE runs.

The general principle of operation is to use the scanning unit of a boundary-scan device as a virtual ATE test channel to drive the excitation of a non-boundary-scan logic circuit and then test the response. Moreover, it is possible to combine the virtual channel and the real ATE channel for driving and testing. When testing individual devices or clusters, the key task is to define the inputs and outputs of the test targets.

The boundary-scan test station is located in the production line process between ICT and FCT testing.

Designed to:

-Complement ICT where necessary, reduce ICT fixture costs with its high coverage, and improve test stability and reliability;

-Significantly reduce FCT test time and test cost.

Fullerton Relay

Ltd. is a NI alliance, agent, system integrator, mainly NIGPIB, NILABVIEW, NIDAQ, NI boards, NI data acquisition cards and other products. The company has a full set of hardware and software for product testing should be run solutions, the development scope includes ICT, Boundary Scan, functional testing, system testing. Business covers Shenzhen, Guangzhou, Zhuhai, Foshan, Nanjing, Hangzhou, Xiamen, Xi'an, Chengdu, Wuhan, Chongqing, Beijing and other places.

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